TLK10031 Datasheet, PDF (31/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
7.4.4 General Purpose SERDES Receive Data Path
With the device configured to operate in the normal transceiver (mission) mode, the high speed to low
speed (receive) data path is shown in the lower half of Figure 7-10. 8B/10B encoded serial data
(HSRXAP*P/N) is received by the high speed side SERDES and deserialized into 20-bit parallel data. The
data is then byte aligned, 8B/10B decoded into 16-bit parallel data, and then delivered to a receive FIFO.
The receive FIFO in turn delivers 32-bit parallel data to the Lane Alignment Master which splits the data
into the same number of lanes as configured on the transmit data path. The lane data is then 8B/10B
encoded and the resulting 10-bit parallel data for each lane is input to the low speed side SERDES for
serialization and output through the OUTAP*P/N pins.
7.4.5 Channel Synchronization
As in the 10GBASE-KR mode, the channel synchronization block is used in the 10G General Purpose
SERDES mode to align received serial data to a defined byte boundary. The channel synchronization
block detects the comma pattern found in the K28.5 character, and follows the synchronization flowchart
shown in Figure 7-3.
7.4.6 8B/10B Encoder and Decoder
As in the 10GBASE-KR and 1GBASE-KX modes, the 8B/10B encoder and decoder blocks are used to
convert between 10-bit (encoded) and 8-bit (unencoded) data words.
7.4.7 Lane Alignment Scheme for 8b/10b General Purpose Serdes Mode
Lower rate multi-lane serial signals must be byte aligned and lane aligned such that high speed
multiplexing (proper reconstruction of higher rate signal) is possible. For that reason, the TLK10031
implements a special lane alignment scheme on the low speed (LS) side for 8b/10b data that does not
contain XAUI alignment characters.
During lane alignment, a proprietary pattern (or a custom comma compliant data stream) is sent by the LS
transmitter to the LS receiver on each active lane. This pattern allows the LS receiver to both delineate
byte boundaries within a lower speed lane and align bytes across the lanes (2 or 4) such that the original
higher rate data ordering is restored.
Lane alignment completes successfully when the LS receiver asserts a “Link Status OK” signal monitored
by the LS transmitter on the link partner device such as an FPGA. The TLK10031 sends out the “Link
Status OK” signals through the LS_OK_OUT_A output pins, and monitors the “Link Status OK” signals
from the link partner device through the LS_OK_IN_A input pins. If the link partner device does not need
the TLK10031 Lane Alignment Master (LAM) to send proprietary lane alignment pattern, LS_OK_IN_A can
be tied high on the application board or set through MDIO register bits.
The lane alignment scheme is activated under any of the following conditions:
• Device/System power up (after configuration/provisioning)
• Loss of channel synchronization assertion on any enabled LS lane
• Loss of signal assertion on any enabled LS lane
• LS SERDES PLL Lock indication deassertion
• After device configuration change
• After software determined LS 8B/10B decoder error rate threshold exceeded
• After device reset is deasserted
• Any time the LS receiver deasserts “Link Status OK”.
• Presence of reoccurring higher level / protocol framing errors
All the above conditions are selectable through MDIO register provisioning.
The block diagram of the lane alignment scheme is shown in Figure 7-11.
Copyright © 2015, Texas Instruments Incorporated
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