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| TLK10031 Datasheet, PDF (38/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver | |||
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TLK10031
SLLSEL3A â JULY 2015 â REVISED AUGUST 2015
www.ti.com
Figure 7-13. General Purpose SERDES Mode Latency
7.4.12.1 Clocking Architecture (All Modes)
A simplified clocking architecture for the TLK10031 is captured in Figure 7-14. The device has an option of
operating with a differential reference clock provided either on pins REFCLK0P/N or REFCLK1P/N. The
choice is made either through MDIO or through REFCLK_SEL pins. The low speed side SERDES, high
speed side SERDES and the associated part of the digital core can operate from the same or different
reference clock.
38
Detailed Description
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