TLK10031 Datasheet, PDF (28/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
7.4.2 1GBASE-KX Mode
A simplified block diagram of the 1GBASE-KX data path is shown in Figure 7-8.
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INA0P
INA0N
Test Pattern
Generation
HSTXAP
HSTXAN
Test Pattern
Verification
Test Pattern
Verification
OUTA0P
OUTA0N
Test Pattern
Generation
Figure 7-8. A Simplified Block Diagram of the 1GKX Data Path
HSRXAP
HSRXAN
7.4.2.1 Channel Sync Block
This block is used to align the deserialized signals to the proper 10-bit word boundaries. The Channel
Sync block generates a synchronization flag indicating incoming data is synchronized to the correct word
boundary. This module implements the synchronization state machine found in Figure 36-9 of the IEEE
802.3-2008 Standard. A synchronization status signal, latched low, is available to indicate synchronization
errors.
7.4.2.2 8b/10b Encoder and Decoder Blocks
As in the 10GBASE-KR operating mode, these blocks are used to convert between 10-bit (encoded) data
and 8-bit data words. They can be optionally bypassed. A code invalid signal, latched low, is available to
indicate 8b/10b encode and decode errors.
7.4.2.3 TX CTC
The transmit clock tolerance compensation (CTC) block acts as a FIFO with add and delete capabilities,
adding and deleting 2 cycles each time to support ±200ppm during IFG (no errors) between the read and
write clocks. This block implements a 12 deep asynchronous FIFO with a usable space 8 deep. It has two
separate pointer tracking systems. One determines when to delete or insert and another determines when
to reset. Inserts and deletes are only allowed during non-errored inter-frame gaps and occurs 2 cycles at a
time. It has an auto reset feature once collision occurs. If a collision occurs, the indication is latched high
until read by MDIO.
7.4.2.4 1GBASE-KX Line Rate, PLL Settings, and Reference Clock Selection
When the TLK10031 is configured to operate in the 1GBASE-KX mode, the available line rates, reference
clock frequencies, and corresponding PLL multipliers are summarized in Table 7-3.
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