TLK10031 Datasheet, PDF (6/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
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PIN
NAME
MDIO
TDI
TDO
TMS
TCK
TRST_N
TESTEN
GPI0
AMUX0
AMUX1
NO.
J7
C8
D6
B8
D8
E5
L10
L8, J4,
J10
C11
D4
Pin Description - Signal Pins (continued)
I/O
TYPE
Input/ Output
LVCMOS 1.5V/1.8V
VDDO1 25Ω Driver
Input LVCMOS
1.5V/1.8V VDDO0
(Internal Pullup)
Output LVCMOS
1.5V/1.8V VDDO0
50Ω Driver
Input LVCMOS
1.5V/1.8V VDDO0
(Internal Pullup)
Input LVCMOS
with Hysteresis
1.5V/1.8V VDDO0
Input LVCMOS
1.5V/1.8V VDDO0
(Internal Pulldown)
Input LVCMOS
1.5V/1.8V VDDO1
Input LVCMOS
1.5V/1.8V VDDO1
Analog I/O
Analog I/O
DESCRIPTION
MDIO Data I/O. MDIO interface data input/output signal for the MDIO interface. This
signal must be externally pulled up to VDDO using a 2-kΩ resistor.
During device reset (RESET_N asserted low) this pin is floating. During software initiated
power down the management interface remains active for control register writes and
reads. Certain status bits will not be deterministic as their generating clock source may be
disabled as a result of asserting either power down input signal. During pin based power
down (PDTRXA_N asserted low), this pin is floating. During register based power down,
this pin is driven normally.
JTAG Input Data. TDI is used to serially shift test data and test instructions into the
device during the operation of the test port. In system applications where JTAG is not
implemented, this input signal may be left floating.
During pin based power down (PDTRXA_N asserted low), this pin is not pulled up. During
register based power down, this pin is pulled up normally.
JTAG Output Data. TDO is used to serially shift test data and test instructions out of the
device during operation of the test port. When the JTAG port is not in use, TDO is in a
high impedance state.
During device reset (RESET_N asserted low) this pin is floating. During pin based power
down (PDTRXA_N asserted low), this pin is not pulled up. During register based power
down, this pin is pulled up normally.
JTAG Mode Select. TMS is used to control the state of the internal test-port controller. In
system applications where JTAG is not implemented, this input signal can be left
unconnected.
During pin based power down (PDTRXA_N asserted low), this pin is not pulled up. During
register based power down, this pin is pulled up normally.
JTAG Clock. TCK is used to clock state information and test data into and out of the
device during boundary scan operation. In system applications where JTAG is not
implemented, this input signal should be grounded.
JTAG Test Reset. TRST_N is used to reset the JTAG logic into system operational
mode. This input can be left unconnected in the application and is pulled down internally,
disabling the JTAG circuitry. If JTAG is implemented on the application board, this signal
should be deasserted (high) during JTAG system testing, and otherwise asserted (low)
during normal operation mode.
During pin based power down (PDTRXA_N asserted low), this pin is not pulled up. During
register based power down, this pin is pulled up normally.
Test Enable. This signal is used during the device manufacturing process. It should be
grounded through a resistor in the device application board. The application board should
allow the flexibility of easily reworking this signal to a high level if device debug is
necessary (by including an uninstalled resistor to VDDO).
General Purpose Input. his signal is used during the device manufacturing process. It
should be grounded through a resistor on the device application board.
SERDES Analog Testability I/O. This signal is used during the device manufacturing
process. It should be left unconnected in the device application.
SERDES Analog Testability I/O. This signal is used during the device manufacturing
process. It should be left unconnected in the device application.
6
Pin Configuration and Functions
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