TLK10031 Datasheet, PDF (58/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
7.5.2.3 HS_SERDES_CONTROL_1 (register: 0x0002 ) (default: 0x831D) (device address: 0x1E)
Figure 7-43. HS_SERDES_CONTROL_1 Register
15
14
13
12
11
10
9
8
RESERVED
HS_LOOP_BANDWIDTH[1:0]
(RXG)
R/W
R/W
7
6
5
4
3
2
1
0
RESERVED
HS_VRANGE
(RXG
RESERVED
HS_ENPLL
(RXG)
HS_PLL_MULT[3:0]
(RXG)
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
15:10
9:8
7
6
5
4
3:0
Table 7-14. HS_SERDES_CONTROL_1 Field Description
Field
HS_LOOP_BANDWIDTH[1:0]
(RXG)
RESERVED
HS_VRANGE
(RXG)
RESERVED
HS_ENPLL
(RXG)
HS_PLL_MULT[3:0]
(RXG)
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
For TI use only (Default 6’b100000)
HS Serdes PLL Loop Bandwidth settings
00 = Medium Bandwidth
01 = Low Bandwidth
10 = High Bandwidth
11 = Ultra High Bandwidth. (Default 2'b11)
For TI use only (Default 1’b0)
HS Serdes PLL VCO range selection.
0 = VCO runs at higher end of frequency range (Default 1’b0)
1 = VCO runs at lower end of frequency range
This bit needs to be set HIGH if VCO frequency (REFCLK *HS_PLL_MULT) is below 2.5
GHz.
For TI use only (Default 1’b0)
HS Serdes PLL enable control. HS Serdes PLL is automatically disabled when
PD_TRXx_N is asserted LOW or when register bit 1E.0001 bit 15 is set HIGH.
0 = Disables PLL in HS serdes
1 = Enables PLL in HS serdes (Default 1’b1)
HS Serdes PLL multiplier setting (Default 4’b1101).
Refer : Table 7-15 HS PLL multiplier control
Value
0000
0001
0010
0011
0100
0101
0110
0111
Table 7-15. HS PLL Multiplier Control
HS_PLL_MULT[3:0]
PLL Multiplier factor
Reserved
Reserved
4x
5x
6x
8x
8.25x
10x
Value
1000
1001
1010
1011
1100
1101
1110
1111
HS_PLL_MULT[3:0]
PLL Multiplier factor
12x
12.5x
15x
16x
16.5x
20x
25x
Reserved
58
Detailed Description
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