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TLK10031 Datasheet, PDF (84/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver
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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
7.5.2.32 EXT_ADDRESS_CONTROL (register = 0x001E) (default = 0x0000) (device address: 0x1E)
Figure 7-72. EXT_ADDRESS_CONTROL Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
EXT_ADDR_CONTROL[15:0]
(XG)
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-53. EXT_ADDRESS_CONTROL Field Descriptions
Bit Field
15:0 EXT_ADDR_CONTROL[15:0]
(XG)
Type Reset
RW
Description
Applicable in Clause 22 mode only. This register should be written with the extended
register address to be written/read. Contents of address written in this register can be
accessed from Reg 1E.0x001F (Default 16’h0000)
7.5.2.33 EXT_ADDRESS_DATA (register = 0x001F) (default = 0x0000) (device address: 0x1E)
Figure 7-73. EXT_ADDRESS_DATA Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
EXT_ADDR_DATA[15:0]
(XG)
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
15:0 EXT_ADDR_DATA[15:0]
(XG)
Table 7-54. EXT_ADDRESS_DATA Field Descriptions
Type Reset
RW
Description
Applicable in Clause 22 mode only. This register contains the data associated with the
register address written in Register 1E.0x001E
The registers below can be accessed directly through Clause 45 or indirectly through Clause 22.
Contains mode specific control/status registers.
7.5.2.34 VS_10G_LN_ALIGN_ACODE_P (register =0x8003) (default = 0x0283)
(device address: 0x1E)
Figure 7-74. VS_10G_LN_ALIGN_ACODE_P Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
LN_ALIGN_ACODE_P[9:0] (G)
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-55. VS_10G_LN_ALIGN_ACODE_P Field Descriptions
Bit
15:10
9:0
Field
RESERVED
LN_ALIGN_ACODE_P[9:0]
(G)
Type
RW
RW
Reset
Description
For TI use only. Always reads 0.
10 bit Alignment character to be matched (Default 10’h283)
84
Detailed Description
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