TLK10031 Datasheet, PDF (112/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
7.5.3.40 KR_VS_TX_CRCJ_ERR_COUNT_1 (register = 0x8019) (default = 0xFFFF)
(device address: 0x01)
Figure 7-127. KR_VS_TX_CRCJ_ERR_COUNT_1 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TX_TPV_CR_CJ_ERR_COUNT[31:16]
(R)
COR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-109. KR_VS_TX_CRCJ_ERR_COUNT_1 Field Descriptions
Bit Field
15:0 TX_TPV_CR_CJ_ERR_COUNT[31:16]
(R)
Type Reset Description
COR
Error Counter for CR/CJ test pattern verification on Tx side. MSBs [31:16]
7.5.3.41 KR_VS_TX_CRCJ_ERR_COUNT_2 (register = 0x801A) (default = 0xFFFD)
(device address: 0x01)
Figure 7-128. KR_VS_TX_CRCJ_ERR_COUNT_2 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TX_TPV_CR_CJ_ERR_COUNT[15:0]
(R)
COR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-110. KR_VS_TX_CRCJ_ERR_COUNT_2 Field Descriptions
Bit Field
15:0 TX_TPV_CR_CJ_ERR_COUNT[15:0]
(R)
Type
COR
Reset
Description
Error Counter for CR/CJ test pattern verification on Tx side. MSBs [15:0]
7.5.3.42 KR_VS_TX_LN0_HLM_ERR_COUNT (register = 0x801B) (default = 0xFFFD)
(device address: 0x01)
Figure 7-129. KR_VS_TX_LN0_HLM_ERR_COUNT Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TX_TPV_LN0_ERR_COUNT[15:0]
(R)
COR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-111. KR_VS_TX_LN0_HLM_ERR_COUNT Field Descriptions
Bit Field
15:0 TX_TPV_LN0_ERR_COUNT[15:0]
(R)
Value
COR
Reset
Description
Error Counter for H/L/M test pattern verification on Lane 0 of Tx side
112 Detailed Description
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