TLK10031 Datasheet, PDF (106/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
7.5.3.26 KR_VS_TP_VER_CONTROL (register = 0x8003) (default = 0x0000)
(device address: 0x01)
Figure 7-113. KR_VS_TP_VER_CONTROL Register
15
14
RESERVED
RW
13
12
TX_TPV_HLM_TEST_
SEL[1:0]
(R)
RW
11
TX_TPV_CRPAT_T
EST_EN
(R)
RW
10
TX_TPV_CJPAT_T
EST_EN
(R)
RW
9
TX_TPV_10GFC_T
EST_EN
(R)
RW
8
TX_TPV_HLM_TES
T_EN
(R)
RW
7
6
5
4
3
2
1
0
RESERVED
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-95. KR_VS_TP_VER_CONTROL Field Descriptions
Bit
15:14
13:12
Name
RESERVED
TX_TPV_HLM_TEST_SEL[1:0]
(R)
11 TX_TPV_CRPAT_TEST_EN
(R)
10 TX_TPV_CJPAT_TEST_EN
(R)
9 TX_TPV_10GFC_TEST_EN
(R)
8 TX_TPV_HLM_TEST_EN
(R)
7:0 RESERVED
Type
RW
RW
Reset
RW
RW
RW
RW
RW
Description
For TI use only. Always reads 0.
XAUI based test pattern selection on LS side. See Test pattern procedures for more
information.
00 = High Frequency test pattern(Default 2’b00)
01 = Low Frequency test pattern
10 = Mixed Frequency test pattern
11 = Normal operation
XAUI based test pattern selection on LS side. See Test pattern procedures for more
information.
0 = Normal operation. (Default 1’b0)
1 = Enables CRPAT test pattern verification
XAUI based test pattern selection on LS side. See Test pattern procedures for more
information.
0 = Normal operation. (Default 1’b0)
1 = Enables CJPAT test pattern verification
XAUI based test pattern selection on LS side. See Test pattern procedures for more
information.
0 = Normal operation. (Default 1’b0)
1 = Enables 10 GFC CJPAT test pattern verification
XAUI based test pattern selection on LS side. See Test pattern procedures for more
information.
0 = Normal operation. (Default 1’b0)
1 = Enables HL/M test pattern verification
For TI use only(Default 8’b00000000)
7.5.3.27 KR_VS_CTC_ERR_CODE_LN0 (register = 0x8005) (default = 0xCE00)
(device address: 0x01)
Figure 7-114. KR_VS_CTC_ERR_CODE_LN0 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
KR_CTC_ERR_CODE_LN0
(R)
RESERVED
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-96. KR_VS_CTC_ERR_CODE_LN0 Field Descriptions
Bit Name
15:7 KR_CTC_ERR_CODE_LN0
(R)
6:0 RESERVED
Type Reset
RW
RW
Description
Applicable in 10G-KR mode only. XGMII code to be transmitted in case of
error condition. This applies to both TX and RX data paths. The msb is the
control bit; remaining 8 bits constitute the error code. The default value for
lane 0 corresponds to 8’h9C with the control bit being 1’b1. The default values
for lanes 0~3 correspond to ||LF||
For TI use only. Always reads 0.
106 Detailed Description
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