TLK10031 Datasheet, PDF (72/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
7.5.2.15 CLK_CONTROL (register: 0x000D) (default: 0x2F80) (device address: 0x1E)
Figure 7-55. CLK_CONTROL Register
15
14
13
12
11
10
9
8
RESERVED
CLKOUT_ EN
(RXG)
CLKOUT_POW
ERDOWN
(RXG)
RESERVED
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
CLKOUT_DIV[3:0]
(RXG)
RCLKOUT_SEL[3:0]
(RXG)
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
15:14
13
Field
RESERVED
CLKOUT_ EN
(RXG)
12 CLKOUT_POWERDOWN
(RXG)
11:8 RESERVED
7:4 CLKOUT_DIV[3:0]
(RXG)
3:0 CLKOUT_SEL[3:0]
(RXG)
Table 7-36. CLK_CONTROL Field Description
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
1
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
00x0
00x1
010x
0110
0111
10x0
10x1
110x
1110
1111
Description
For TI use only. Always reads 0.
Output clock enable.
Holds CLKOUTx_P/N output to a fixed value.
Allows CLKOUTx_P/N output to toggle normally. (Default 1’b1)
Normal operation (Default 1’b0)
Enable CLKOUTx_P/N Power Down.
For TI use only. (Default 4'b1111)
CLKOUT Output clock divide setting. This value is used to divide selected clock (Selected
using CLKOUT_SEL) before giving it out onto respective channel CLKOUTA_P/N.
0000 = Divide by 1
Reserved
Reserved
Reserved
Divide by 2
Reserved
Reserved
Reserved
Divide by 4 (Default 4'b1000)
Divide by 8
Divide by 16
Reserved
Divide by 5
Divide by 10
Divide by 20
Divide by 25
CLKOUT Output clock select. Selects Recovered clock sent out on CLKOUTx_P/N pins
(Default 4'b0000)
Selects HS recovered byte clock as output clock
Selects HS transmit byte clock as output clock
Selects HSRX VCO divide by 4 clock as output clock
Selects LS recovered byte clock as output clock
Selects LS transmit byte clock as output clock
Reserved
Reserved
Reserved
Reserved
Reserved
72
Detailed Description
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