TLK10031 Datasheet, PDF (68/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
7.5.2.11 LS_OVERLAY_CONTROL (register: 0x000A) (default: 0x4000)
(device address: 0x1E)
Figure 7-51. LS_OVERLAY_CONTROL Register
15
14
13
12
11
10
9
8
RESERVED
LS_PLL_LOCK
_OVERLAY
(RXG)
LS_CH_SYNC_OVERLAY_LN[3:0]
(RXG)
R/W
R/W
R/W
7
6
5
4
3
2
1
0
LS_INVALID_CODE_OVERLAY_LN[3:0]
(RXG)
LS_LOS_OVERLAY_LN[3:0]
(RXG)
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-32. LS_OVERLAY_CONTROL Field Description
Bit
15:13
12
Field
RESERVED
LS_PLL_LOCK_OVERLAY
(RXG)
11:8 LS_CH_SYNC_OVERLAY_LN[3:0]
(RXG)
7:4 LS_INVALID_CODE_OVERLAY_LN[3:0]
(RXG)
3:0 LS_LOS_OVERLAY_LN[3:0]
(RXG)
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset Description
For TI use only (Default 3’b010)
0 LOSA pin does not reflect loss of LS SERDES PLL lock status
(Default 1’b0)
1 Allows LS SERDES loss of PLL lock status to be reflected on LOSA
pin
[3] Corresponds to Lane 3, [2] Corresponds to Lane 2
[1] Corresponds to Lane 1, [0] Corresponds to Lane 0
0 LOSA pin does not reflect LS Serdes lane loss of synchronization
condition (Default 1’b0)
1 Allows LS Serdes lane loss of synchronization condition to be
reflected on LOSA pin
0 [3] Corresponds to Lane 3, [2] Corresponds to Lane 2
[1] Corresponds to Lane 1, [0] Corresponds to Lane 0
0 LOSA pin does not reflect LS Serdes lane invalid code condition
(Default 1’b0)
1 Allows LS Serdes lane invalid code condition to be reflected on LOSA
pin
[3] Corresponds to Lane 3, [2] Corresponds to Lane 2
[1] Corresponds to Lane 1, [0] Corresponds to Lane 0
0 LOSA pin does not reflect LS Serdes lane Loss of signal condition
(Default 1’b0)
1 Allows LS Serdes lane Loss of signal condition to be reflected on
LOSA pin
68
Detailed Description
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