TLK10031 Datasheet, PDF (36/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
Table 7-4, Table 7-5, and Table 7-6 indicate two possible reference clock frequencies for CPRI/OBSAI
applications: 153.6MHz and 122.88MHz, which can be used based on the application preference. The
SERDES PLL Multiplier (MPY) has been given for each reference clock frequency respectively. The low
speed side and the high speed side SERDES use the same reference clock frequency.
For other line rates not shown in Table 7-4, Table 7-5, or Table 7-6, valid reference clock frequencies can
be selected with the help of the information provided in Table 7-7 and Table 7-8 for the low speed and
high speed side SERDES. The reference clock frequency has to be the same for the two SERDES and
must be within the specified valid ranges for different PLL multipliers.
Table 7-7. Line Rate and Reference Clock Frequency Ranges for the Low Speed Side SERDES (General
Purpose Mode)
SERDES PLL
Multiplier (MPY)
Reference Clock (MHz)
Min
Max
4
250
425
5
200
425
6
166.667
416.667
8
125
312.5
10
122.88
250
12
122.88
208.333
12.5
122.88
200
15
122.88
166.667
20
122.88
125
RateScale: Full Rate = 0.5, Half Rate = 1, Quarter Rate = 2
Full Rate (Gbps)
Min
Max
2
3.4
2
4.25
2
5
2
5
2.4576
5
2.94912
5
3.072
5
3.6864
5
4.9152
5
Half Rate (Gbps)
Min
Max
1
1.7
1
2.125
1
2.5
1
2.5
1.2288
2.5
1.47456
2.5
1.536
2.5
1.8432
2.5
2.4576
2.5
Quarter Rate (Gbps)
Min
Max
0.5
0.85
0.5
1.0625
0.5
1.25
0.5
1.25
0.6144
1.25
0.73728
1.25
0.768
1.25
0.9216
1.25
1.2288
1.25
Table 7-8. Line Rate and Reference Clock Frequency Ranges for the High Speed Side SERDES (General
Purpose Mode)
SERDES PLL
Multiplier (MPY)
Reference Clock (MHz)
Min
Max
Full Rate (Gbps)
Min
Max
4
375
425
6
6.8
5
300
425
6
8.5
6
250
416.667
6
10
8
187.5
312.5
6
10
10
150
250
6
10
12
125
208.333
6
10
12.5
153.6
200
7.68
10
15
122.88
166.667
7.3728
10
16
122.88
156.25
7.86432
10
20
122.88
125
9.8304
10
RateScale: Full Rate = 0.25, Half Rate = 0.5, Quarter Rate = 1, Eighth Rate = 2
Half Rate (Gbps)
Min
Max
3
3.4
3
4.25
3
5
3
5
3
5
3
5
3.84
5
3.6864
5
3.932
5
4.9152
5
Quarter Rate (Gbps)
Min
Max
1.5
1.7
1.5
2.125
1.5
2.5
1.5
2.5
1.5
2.5
1.5
2.5
1.92
2.5
1.8432
2.5
1.966
2.5
2.4576
2.5
Eighth Rate (Gbps)
Min
Max
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.2288
1.0625
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
For example, in the 2:1 operation mode, if the low speed side line rate is 1.987Gbps, the high-speed side
line rate will be 3.974Gbps. The following steps can be taken to make a reference clock frequency
selection:
1. Determine the appropriate SERDES rate modes that support the required line rates. Table 7-7 shows
that the 1.987Gbps line rate on the low speed side is only supported in the half rate mode (RateScale
= 1). Table 7-8 shows that the 3.974Gbps line rate on the high speed side is only supported in the half
rate mode (RateScale = 1).
2. For each SERDES side, and for all available PLL multipliers (MPY), compute the corresponding
reference clock frequencies using the formula:
Reference Clock Frequency = (LineRate x RateScale)/MPY
The computed reference clock frequencies are shown in Table 7-9 along with the valid minimum and
maximum frequency values.
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