TLK10031 Datasheet, PDF (87/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
7.5.2.40 DSR_ON_CHAR_CONTROL (register = 0x802D) (default = 0x02FD)
(device address: 0x1E)
Figure 7-80. DSR_ON_CHAR_CONTROL Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
DSR_ON_CHAR[9:0]
(XG)
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
15:10
9:0
Field
RESERVED
DSR_ON_CHAR[9:0]
(XG)
Table 7-61. DSR_ON_CHAR_CONTROL Field Descriptions
Type
RW
RW
Reset
Description
For TI use only. Always reads 0.
Applicable only in 1GKX and 10G modes. 10 bit data pattern to trigger ON condition if
matched on receive side (Default 10’h2FD)
7.5.2.41 DSR_OFF_CHAR_CONTROL (register = 0X802E) (default = 0x02FD)
(device address: 0x1E)
Figure 7-81. DSR_OFF_CHAR_CONTROL Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
DSR_OFF_CHAR[9:0]
(XG)
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
15:10
9:0
Field
RESERVED
DSR_OFF_CHAR[9:0]
(XG)
Table 7-62. DSR_OFF_CHAR_CONTROL Field Descriptions
Type
RW
RW
Reset
Description
For TI use only. Always reads 0.
Applicable only in 1GKX and 10G modes. 10 bit data pattern to trigger OFF condition if
matched on receive side (Default 10’h2FD)
7.5.2.42 DSR_STUFF_CHAR_CONTROL (register = 0x802F) (default = 0x0207)
(device address: 0x1E)
Figure 7-82. DSR_STUFF_CHAR_CONTROL Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
DSR_STUFF_CHAR[9:0]
(G)
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-63. DSR_STUFF_CHAR_CONTROL Field Descriptions
Bit
15:10
9:0
Field
RESERVED
DSR_STUFF_CHAR[9:0]
(G)
Type
RW
RW
Reset
Description
For TI use only. Always reads 0.
Applicable only in 10G mode. 10 bit data pattern to stuff the output of data switch on receive
side (Default 10’h207)
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