TLK10031 Datasheet, PDF (40/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
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7.4.14 Serial Loopback Modes
The TLK10031 supports internal loopback of the serial output signals for self-test and system diagnostic
purposes. Loopback mode can be enabled independently for each SERDES via MDIO register bits. When
loopback mode is enabled for a particular SERDES, the serial output data will be internally routed to the
SERDES’s serial input port. The output data will remain available for monitoring on the output pins.
7.4.15 Latency Measurement Function (General Purpose SerDes Mode)
The TLK10031 includes a latency measurement function to support CPRI and OBSAI type applications.
There are two start and two stop locations for the latency counter as shown in Figure 7-16. The start and
stop locations are selectable through MDIO register bits. The elapsed time from a comma detected at an
assigned counter start location to a comma detected at an assigned counter stop location is measured
and reported through the MDIO interface. The following three control characters (containing commas) are
monitored:
1. K28.1 (control = 1, data = 0x3C)
2. K28.5 (control = 1, data = 0xBC)
3. K28.7 (control = 1, data = 0xFC).
The first comma found at the assigned counter start location will start up the latency counter. The first
comma detected at the assigned counter stop location will stop the latency counter. The 20-bit latency
counter result of this measurement is readable through the MDIO interface. The accuracy of the
measurement is a function of the serial bit rate. The register will return a value of 0xFFFFF if the duration
between transmit and receive comma detection exceeds the depth of the counter. Only one measurement
value is stored internally until the 20-bit results counter is read. The counter will return zero in cases
where a transmit comma was never detected (indicating the results counter never began counting). In
addition, the stopwatch counter can be configured to be started or stopped manually based on the state of
the PRTAD0 pin (see MDIO register map for details).
INA0P/N
INA1P/N
INA2P/N
INA3P/N
OUTA0P/N
OUTA1P/N
OUTA2P/N
OUTA3P/N
10
10
LS PRBS
Verifier
10
10
10
10
10
10
32
16
TX FIFO
Pattern ¹⁶
Generator
16
Stop
Counter
20 ^{HS PRBS}
Generator
Low
Speed
Side
SERDES
10
10
LS PRBS ¹⁰
Generator ₁₀
Start
Counter
Latency
Counter
Stop
Counter
Transmit Data Path Covered
Receive Data Path Covered
Start
Counter
High
Speed
Side
SERDES
10
32
16
10
RX FIFO
20 ^{HS PRBS}
Verifier
10
10
Pattern
Verifier
Figure 7-16. Location of TX and RX Comma Character Detection
HSTXAP /N
HSRXAP /N
40
Detailed Description
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