TLK10031 Datasheet, PDF (75/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
7.5.2.18 HS_ERROR_COUNTER (register: 0x0010) (default: 0x0FFFD) (device address: 0x1E)
Figure 7-58. HS_ERROR_COUNTER Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
HS_ERR_COUNT[15:0]
(RXG)
COR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
15:0 HS_ERR_COUNT[15:0]
(RXG)
Table 7-39. HS_ERROR_COUNTER Field Description
Type
COR
Reset
0
Description
In functional mode, this counter reflects number of invalid code words (includes disparity errors)
received by decoder. In 10GKR mode, reading this register also clears value in 03.0021 bits 7:0.
In 10GKR mode, default value for this register is 16’h0000.
In HS test pattern verification mode , this counter reflects error count for the test pattern selected
through 1E.000B bits 10:8
When PRBS_EN pin is set, this counter reflects error count for selected PRBS pattern.
Counter value cleared to 16’h0000 when read.
7.5.2.19 LS_LN0_ERROR_COUNTER (register: 0x0011) (default: 0xFFFD) (device address: 0x1E)
Figure 7-59. LS_LN0_ERROR_COUNTER Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
LS_LN0_ERR_COUNT[15:0]
(RXG)
COR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
15:0 LS_LN0_ERR_COUNT[15:0]
(RXG)
Table 7-40. LS_LN0_ERROR_COUNTER Field Description
Type
COR
Reset
0
Description
Lane 0 Error counter
In 10GKR/1GKX functional modes, this counter reflects number of invalid code words (includes
disparity errors) received by decoder
In 10G functional mode, this counter reflects number of invalid code words (includes disparity
errors) received by decoder in lane alignment slave.
In LS test pattern verification mode , this counter reflects error count for the test pattern selected
through 1E.000B bits 5:4
Counter value cleared to 16’h0000 when read.
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Detailed Description
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