C8051F80X_14 Datasheet, PDF (99/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
Table 17.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
CS0CF
CS0MX
CS0SE
CS0SS
DERIVID
Address
Description
0x9E CS0 Configuration
0x9C CS0 Mux
0xBA Auto Scan End Channel
0xB9 Auto Scan Start Channel
0xAD Derivative Identification
DPH
DPL
EIE1
EIE2
EIP1
EIP2
0x83
0x82
0xE6
0xE7
0xF3
0xF4
Data Pointer High
Data Pointer Low
Extended Interrupt Enable 1
Extended Interrupt Enable 2
Extended Interrupt Priority 1
Extended Interrupt Priority 2
FLKEY
HWID
IE
IP
IT01CF
OSCICL
OSCICN
OSCXCN
P0
P0MASK
P0MAT
P0MDIN
P0MDOUT
P0SKIP
P1
P1MASK
0xB7
0xB5
0xA8
0xB8
0xE4
0xB3
0xB2
0xB1
0x80
0xFE
0xFD
0xF1
0xA4
0xD4
0x90
0xEE
Flash Lock And Key
Hardware Identification
Interrupt Enable
Interrupt Priority
INT0/INT1 Configuration
Internal Oscillator Calibration
Internal Oscillator Control
External Oscillator Control
Port 0 Latch
Port 0 Mask
Port 0 Match
Port 0 Input Mode Configuration
Port 0 Output Mode Configuration
Port 0 Skip
Port 1 Latch
P0 Mask
Page
76
81
78
78
96
88
88
107
108
109
110
119
95
105
106
112
131
132
134
153
151
151
154
154
155
155
152
Rev. 1.0
99