C8051F80X_14 Datasheet, PDF (180/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
26. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I²C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple mas-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. The SMBus peripheral can be fully driven by
software (i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware slave address
recognition and automatic ACK generation can be enabled to minimize software overhead. A block dia-
gram of the SMBus peripheral and the associated SFRs is shown in Figure 26.1.
SMB0CN
MT S S A A A S
AXT TCRC I
SMAOK B K
TO
RL
ED
QO
RE
S
T
SMB0CF
E I BESSSS
N N U XMMMM
SHSTBBBB
M YHT FCC
B
OOT S S
LEE1 0
D
00
T0 Overflow
01
T1 Overflow
10
TMR2H Overflow
11
TMR2L Overflow
Interrupt
Request
SMBUS CONTROL LOGIC
Arbitration
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
Hardware Slave Address Recognition
Hardware ACK Generation
IRQ Generation
Data Path
Control
SCL
Control
SDA
Control
SCL
FILTER
N
C
R
O
S
S
B
A
R
SSSSSSSG
L L L L L L LC
VVVVVVV
6543210
SMB0ADR
SSSSSSSE
L L L L L L LH
VVVVVVVA
MMMMMMMC
6543210K
SMB0ADM
SMB0DAT
76543210
FILTER
SDA
N
Port I/O
Figure 26.1. SMBus Block Diagram
180
Rev. 1.0