C8051F80X_14 Datasheet, PDF (207/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
SFR Definition 27.2. SBUF0: Serial (UART0) Port Data Buffer
Bit
7
6
5
4
3
2
1
0
Name
SBUF0[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x99
Bit Name
Function
7:0 SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB).
This SFR accesses two registers; a transmit shift register and a receive latch register.
When data is written to SBUF0, it goes to the transmit shift register and is held for
serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
Rev. 1.0
207