C8051F80X_14 Datasheet, PDF (151/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
SFR Definition 23.3. P0MASK: Port 0 Mask Register
Bit
7
6
5
4
3
2
1
0
Name
P0MASK[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xFE
Bit
Name
7:0 P0MASK[7:0]
Function
Port 0 Mask Value.
Selects P0 pins to be compared to the corresponding bits in P0MAT.
0: P0.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin logic value is compared to P0MAT.n.
SFR Definition 23.4. P0MAT: Port 0 Match Register
Bit
7
6
5
4
3
2
1
0
Name
P0MAT[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xFD
Bit
Name
7:0 P0MAT[7:0]
Function
Port 0 Match Value.
Match comparison value used on Port 0 for bits in P0MASK which are set to 1.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
Rev. 1.0
151