C8051F80X_14 Datasheet, PDF (234/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
29.3.5.2. 9-bit through 15-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in N-bit PWM mode (N=9 through 15) should be varied by writing
to an “Auto-Reload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register loca-
tions. The data written to define the duty cycle should be right-justified in the registers. The auto-reload
registers are accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/com-
pare registers are accessed when ARSEL is set to 0.
When the least-significant N bits of the PCA0 counter match the value in the associated module’s cap-
ture/compare register (PCA0CPn), the output on CEXn is asserted high. When the counter overflows from
the Nth bit, CEXn is asserted low (see Figure 29.9). Upon an overflow from the Nth bit, the COVF flag is
set, and the value stored in the module’s auto-reload register is loaded into the capture/compare register.
The value of N is determined by the CLSEL bits in register PCA0PWM. This synchronous update feature
allows software to asynchronously write a new PWM high time, which will then take effect on the following
PWM period.
The 9, 10, 11, 12, 13, 14, or 15-bit PWM mode is selected by setting the ECOMn and PWMn bits in the
PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other
than 8-bits). If the MATn bit is set to 1, the CCFn flag for the module will be set each time a comparator
match (rising edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge),
which will occur every 512 (9-bit), 1024 (10-bit), 2048 (11-bit), 4096 (12-bit), 8192 (13-bit), 16384 (14-bit),
or 32768 (15-bit) PCA clock cycles. The duty cycle for n-Bit PWM Mode (n=9 through 15) is given in
Equation 29.2, where N is the number of bits in the PWM cycle. A 0% duty cycle may be generated by
clearing the ECOMn bit to 0.
Important Note About PCA0CPHn and PCA0CPLn Registers: When writing a 16-bit value to the
PCA0CPn registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn
bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Duty Cycle = ^---2---^N-----–----^P----^C-----^A----0---^C----^P----ⁿ----^
2^N
Equation 29.3. N-Bit PWM Duty Cycle (N=9 through 15)
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn ^ENB
1
PCA0CPMn
PECCMT PE
WC A A A O WC
MO P P T GMC
1 MPN n n n F
6nnn
n
n
0 00x0 x
R/W when
ARSEL = 1
(Auto-Reload)
PCA0CPH:Ln
(right-justified)
R/W when
ARSEL = 0
(Capture/Compare)
PCA0CPH:Ln
(right-justified)
Enable _{N-bit Comparator}
PCA0PWM
AEC
RCO
SOV
EVF
L
ECCC
AL L L
RSSS
1EEE
6LLL
210
x
x
Set “N” bits:
001 = 9 bits
010 = 10 bits
011 = 11 bits
100 = 12 bits
101 = 13 bits
110 = 14 bits
111 = 15 bits
Match _S SET _Q CEXn _Crossbar
Port I/O
R CLR Q
PCA Timebase
PCA0H:L
Overflow of N^th Bit
Figure 29.9. PCA 9-bit through 15-Bit PWM Mode Diagram
234
Rev. 1.0