C8051F80X_14 Datasheet, PDF (67/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
SFR Definition 12.1. CPT0CN: Comparator0 Control
Bit
Name
Type
Reset
7
CP0EN
R/W
0
6
CP0OUT
R
0
5
CP0RIF
R/W
0
4
CP0FIF
R/W
0
3
2
CP0HYP[1:0]
R/W
0
0
1
0
CP0HYN[1:0]
R/W
0
0
SFR Address = 0x9B
Bit
Name
Function
7
CP0EN Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
6 CP0OUT Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
5
CP0RIF Comparator0 Rising-Edge Flag. Must be cleared by software.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
4
CP0FIF Comparator0 Falling-Edge Flag. Must be cleared by software.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.
3:2 CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
Rev. 1.0
67