C8051F80X_14 Datasheet, PDF (5/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
23.1. Port I/O Modes of Operation.......................................................................... 139
23.1.1. Port Pins Configured for Analog I/O...................................................... 139
23.1.2. Port Pins Configured For Digital I/O...................................................... 139
23.1.3. Interfacing Port I/O to 5 V Logic ............................................................ 140
23.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 140
23.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 140
23.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 141
23.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 142
23.3. Priority Crossbar Decoder ............................................................................. 143
23.4. Port I/O Initialization ...................................................................................... 147
23.5. Port Match ..................................................................................................... 150
23.6. Special Function Registers for Accessing and Configuring Port I/O ............. 152
24. Cyclic Redundancy Check Unit (CRC0)............................................................. 159
24.1. 16-bit CRC Algorithm..................................................................................... 160
24.2. 32-bit CRC Algorithm..................................................................................... 161
24.3. Preparing for a CRC Calculation ................................................................... 162
24.4. Performing a CRC Calculation ...................................................................... 162
24.5. Accessing the CRC0 Result .......................................................................... 162
24.6. CRC0 Bit Reverse Feature............................................................................ 166
25. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 167
25.1. Signal Descriptions........................................................................................ 168
25.1.1. Master Out, Slave In (MOSI)................................................................. 168
25.1.2. Master In, Slave Out (MISO)................................................................. 168
25.1.3. Serial Clock (SCK) ................................................................................ 168
25.1.4. Slave Select (NSS) ............................................................................... 168
25.2. SPI0 Master Mode Operation ........................................................................ 168
25.3. SPI0 Slave Mode Operation .......................................................................... 170
25.4. SPI0 Interrupt Sources .................................................................................. 171
25.5. Serial Clock Phase and Polarity .................................................................... 171
25.6. SPI Special Function Registers ..................................................................... 173
26. SMBus................................................................................................................... 180
26.1. Supporting Documents .................................................................................. 181
26.2. SMBus Configuration..................................................................................... 181
26.3. SMBus Operation .......................................................................................... 181
26.3.1. Transmitter Vs. Receiver....................................................................... 182
26.3.2. Arbitration.............................................................................................. 182
26.3.3. Clock Low Extension............................................................................. 182
26.3.4. SCL Low Timeout.................................................................................. 182
26.3.5. SCL High (SMBus Free) Timeout ......................................................... 183
26.4. Using the SMBus........................................................................................... 183
26.4.1. SMBus Configuration Register.............................................................. 183
26.4.2. SMB0CN Control Register .................................................................... 187
26.4.2.1. Software ACK Generation ............................................................ 187
26.4.2.2. Hardware ACK Generation ........................................................... 187
26.4.3. Hardware Slave Address Recognition .................................................. 189
Rev. 1.0
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