C8051F80X_14 Datasheet, PDF (156/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
SFR Definition 23.12. P1MDIN: Port 1 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P1MDIN[7:0]
Type
R/W
Reset
1*
1*
1*
1*
1
1
1
1
SFR Address = 0xF2
Bit
Name
7:0 P1MDIN[7:0]
Function
Analog Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled. In order for the P1.n pin to be in analog mode, there
MUST be a 1 in the Port Latch register corresponding to that pin.
0: Corresponding P1.n pin is configured for analog mode.
1: Corresponding P1.n pin is not configured for analog mode.
Note: P1.4–P1.7 are not available on 16-pin packages, with the reset value of 0000b for
P1MDIN[7:4].
SFR Definition 23.13. P1MDOUT: Port 1 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
P1MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA5
Bit
Name
Function
7:0 P1MDOUT[7:0] Output Configuration Bits for P1.7–P1.0 (respectively).
These bits are ignored if the corresponding bit in register P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
Note: P1.4–P1.7 are not available on 16-pin packages.
156
Rev. 1.0