C8051F80X_14 Datasheet, PDF (15/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
1. System Overview
C8051F80x-83x devices are fully integrated, mixed-signal, system-on-a-chip capacitive sensing MCUs.
Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part
ordering numbers.
High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
Capacitive sense interface with 16 input channels
10-bit 500 ksps single-ended ADC with 16-channel analog multiplexer and integrated temperature sensor
Precision calibrated 24.5 MHz internal oscillator
16 kb of on-chip Flash memory
512 bytes of on-chip RAM
SMBus/I²C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware
Three general-purpose 16-bit timers
Programmable counter/timer array (PCA) with three capture/compare modules
On-chip internal voltage reference
On-chip Watchdog timer
On-chip power-on reset and supply monitor
On-chip voltage comparator
17 general purpose I/O
With on-chip power-on reset, V_DD monitor, watchdog timer, and clock oscillator, the C8051F80x-83x
devices are truly stand-alone, system-on-a-chip solutions. The Flash memory can be reprogrammed even
in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User
software has complete control of all peripherals, and may individually shut down any or all peripherals for
power savings.
The C8051F80x-83x processors include Silicon Laboratories’ 2-Wire C2 Debug and Programming inter-
face, which allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the pro-
duction MCU installed in the final application. This debug logic supports inspection of memory, viewing and
modification of special function registers, setting breakpoints, single stepping, and run and halt commands.
All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins
can be shared with user functions, allowing in-system debugging without occupying package pins.
Each device is specified for 1.8–3.6 V operation over the industrial temperature range (–45 to +85 °C). An
internal LDO regulator is used to supply the processor core voltage at 1.8 V. The Port I/O and RST pins are
tolerant of input signals up to 5 V. See Table 2.1 for ordering information. Block diagrams of the devices in
the C8051F80x-83x family are shown in Figure 1.1 through Figure 1.9.
Rev. 1.0
15