C8051F80X_14 Datasheet, PDF (49/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
8.3.3. Settling Time Requirements
A minimum tracking time is required before each conversion to ensure that an accurate conversion is per-
formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the
the ADC0 sampling capacitance, and the accuracy required for the conversion. In delayed tracking mode,
three SAR clocks are used for tracking at the start of every conversion. For many applications, these three
SAR clocks will meet the minimum tracking time requirements.
Figure 8.3 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 8.1. See Table 7.9 for ADC0 minimum settling time
requirements as well as the mux impedance and sampling capacitor values.
t
=
ln


S^-2---A^{n--}

R_TOTALC_SAMPLE
Equation 8.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R_TOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (10).
MUX Select
Input Pin
R_MUX
RC_Input= R_MUX * C_SAMPLE
C_SAMPLE
Note: See electrical specification tables for R_MUX and C_SAMPLE parameters.
Figure 8.3. ADC0 Equivalent Input Circuits
Rev. 1.0
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