C8051F80X_14 Datasheet, PDF (197/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
Table 26.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
Values Read
Current SMbus State
Values to
Write
Typical Response Options
1110
0
0
X
A master START was gener-
ated.
Load slave address + R/W into
SMB0DAT.
0 0 X 1100
A master data or address byte Set STA to restart transfer.
0 0 0 was transmitted; NACK
received.
Abort transfer.
1 0 X 1110
01X —
Load next data byte into
SMB0DAT.
0 0 X 1100
1100
End transfer with STOP.
01X —
A master data or address byte End transfer with STOP and start 1 1 X —
0 0 1 was transmitted; ACK
another transfer.
received.
Send repeated START.
1 0 X 1110
Switch to Master Receiver Mode 0 0 X 1000
(clear SI without writing new data
to SMB0DAT).
Acknowledge received byte;
Read SMB0DAT.
0 0 1 1000
Send NACK to indicate last byte, 0 1 0 —
and send STOP.
Send NACK to indicate last byte, 1 1 0 1110
and send STOP followed by
START.
1000
1
0
X
A master data byte was
received; ACK requested.
Send ACK followed by repeated 1 0 1 1110
START.
Send NACK to indicate last byte, 1 0 0 1110
and send repeated START.
Send ACK and switch to Master 0 0 1 1100
Transmitter Mode (write to
SMB0DAT before clearing SI).
Send NACK and switch to Mas- 0 0 0 1100
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
Rev. 1.0
197