C8051F80X_14 Datasheet, PDF (11/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
Figure 26.3. SMBus Transaction ........................................................................... 182
Figure 26.4. Typical SMBus SCL Generation ........................................................ 184
Figure 26.5. Typical Master Write Sequence ........................................................ 193
Figure 26.6. Typical Master Read Sequence ........................................................ 194
Figure 26.7. Typical Slave Write Sequence .......................................................... 195
Figure 26.8. Typical Slave Read Sequence .......................................................... 196
27. UART0
Figure 27.1. UART0 Block Diagram ...................................................................... 201
Figure 27.2. UART0 Baud Rate Logic ................................................................... 202
Figure 27.3. UART Interconnect Diagram ............................................................. 203
Figure 27.4. 8-Bit UART Timing Diagram .............................................................. 203
Figure 27.5. 9-Bit UART Timing Diagram .............................................................. 204
Figure 27.6. UART Multi-Processor Mode Interconnect Diagram ......................... 205
28. Timers
Figure 28.1. T0 Mode 0 Block Diagram ................................................................. 212
Figure 28.2. T0 Mode 2 Block Diagram ................................................................. 213
Figure 28.3. T0 Mode 3 Block Diagram ................................................................. 214
Figure 28.4. Timer 2 16-Bit Mode Block Diagram ................................................. 219
Figure 28.5. Timer 2 8-Bit Mode Block Diagram ................................................... 220
29. Programmable Counter Array
Figure 29.1. PCA Block Diagram ........................................................................... 225
Figure 29.2. PCA Counter/Timer Block Diagram ................................................... 226
Figure 29.3. PCA Interrupt Block Diagram ............................................................ 227
Figure 29.4. PCA Capture Mode Diagram ............................................................. 229
Figure 29.5. PCA Software Timer Mode Diagram ................................................. 230
Figure 29.6. PCA High-Speed Output Mode Diagram ........................................... 231
Figure 29.7. PCA Frequency Output Mode ........................................................... 232
Figure 29.8. PCA 8-Bit PWM Mode Diagram ........................................................ 233
Figure 29.9. PCA 9-bit through 15-Bit PWM Mode Diagram ................................. 234
Figure 29.10. PCA 16-Bit PWM Mode ................................................................... 235
Figure 29.11. PCA Module 2 with Watchdog Timer Enabled ................................ 236
30. C2 Interface
Figure 30.1. Typical C2 Pin Sharing ...................................................................... 247
Rev. 1.0
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