C8051F80X_14 Datasheet, PDF (154/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
SFR Definition 23.8. P0MDIN: Port 0 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P0MDIN[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xF1
Bit
Name
7:0 P0MDIN[7:0]
Function
Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled. In order for the P0.n pin to be in analog mode, there
MUST be a ‘1’ in the Port Latch register corresponding to that pin.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
SFR Definition 23.9. P0MDOUT: Port 0 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
P0MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA4
Bit
Name
Function
7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively).
These bits are ignored if the corresponding bit in register P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
154
Rev. 1.0