C8051F80X_14 Datasheet, PDF (221/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
28.2.3. Comparator 0 Capture Mode
The capture mode in Timer 2 allows Comparator 0 rising edges to be captured with the timer clocking from
the system clock or the system clock divided by 12. Timer 2 capture mode is enabled by setting TF2CEN
to 1 and T2SPLIT to 0.
When capture mode is enabled, a capture event will be generated on every Comparator 0 rising edge.
When the capture event occurs, the contents of Timer 2 (TMR2H:TMR2L) are loaded into the Timer 2
reload registers (TMR2RLH:TMR2RLL) and the TF2H flag is set (triggering an interrupt if Timer 2 inter-
rupts are enabled). By recording the difference between two successive timer capture values, the
Comparator 0 period can be determined with respect to the Timer 2 clock. The Timer 2 clock should be
much faster than the capture clock to achieve an accurate reading.
This mode allows software to determine the time between consecutive Comparator 0 rising edges, which
can be used for detecting changes in the capacitance of a capacitive switch, or measuring the frequency of
a low-level analog signal.
T2XCLK
SYSCLK / 12
0
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
External Clock / 8
1
SYSCLK
0
TR2
TCLK _{TMR2L TMR2H}
1
Capture
Comparator 0
Output
TF2CEN
TMR2RLL TMR2RLH
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
T2XCLK
Figure 28.6. Timer 2 Capture Mode Block Diagram
Interrupt
Rev. 1.0
221