C8051F80X_14 Datasheet, PDF (121/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
20.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter Stop mode as soon as the
instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µs.
20.3. Suspend Mode
Suspend mode allows a system running from the internal oscillator to go to a very low power state similar
to Stop mode, but the processor can be awakened by certain events without requiring a reset of the device.
Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the CPU and the high-frequency inter-
nal oscillator, and go into Suspend mode as soon as the instruction that sets the bit completes execution.
All internal registers and memory maintain their original data. Most digital peripherals are not active in Sus-
pend mode. The exception to this is the Port Match feature and Timer 3, when it is run from an external
oscillator source.
The clock divider bits CLKDIV[2:0] in register CLKSEL must be set to "divide by 1" when entering suspend
mode.
Suspend mode can be terminated by five types of events, a port match (described in Section “23.5. Port
Match” on page 150), a Timer 2 overflow (described in Section “28.2. Timer 2” on page 219), a comparator
low output (if enabled), a capacitive sense greater-than comparator event, or a device reset event. In order
to run Timer 3 in suspend mode, the timer must be configured to clock from the external clock source.
When suspend mode is terminated, the device will continue execution on the instruction following the one
that set the SUSPEND bit. If the wake event (port match or Timer 2 overflow) was configured to generate
an interrupt, the interrupt will be serviced upon waking the device. If suspend mode is terminated by an
internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at
address 0x0000.
Note: The device will still enter suspend mode if a wake source is "pending", and the device will not wake on such
pending sources. It is important to ensure that the intended wake source will trigger after the device enters
suspend mode. For example, if a CS0 conversion completes and the interrupt fires before the device is in
suspend mode, that interrupt cannot trigger the wake event. Because port match events are level-sensitive,
pre-existing port match events will trigger a wake, as long as the match condition is still present when the
device enters suspend.
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