C8051F80X_14 Datasheet, PDF (184/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
Table 26.1. SMBus Clock Source Selection
SMBCS1
0
0
1
1
SMBCS0
0
1
0
1
SMBus Clock Source
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 26.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “28. Timers” on page 209.
T_HighMin
=
T_LowMin
=
----------------------1-----------------------
f_{ClockSourceOverflow}
Equation 26.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 26.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 26.2.
BitRate = -^f-^C----^l-^o---^c--^k--^S---^o--^u---^r--^c--^e--^O----^v--^e--^r--^f--^l-^o---^w-
3
Equation 26.2. Typical SMBus Bit Rate
Figure 26.4 shows the typical SCL generation described by Equation 26.2. Notice that T_HIGH is typically
twice as large as T_LOW. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 26.1.
Timer Source
Overflows
SCL
TLow
THigh
SCL High Timeout
Figure 26.4. Typical SMBus SCL Generation
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 26.2 shows the min-
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