C8051F80X_14 Datasheet, PDF (216/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
SFR Definition 28.3. TMOD: Timer Mode
Bit
Name
Type
Reset
7
GATE1
R/W
0
6
C/T1
R/W
0
5
4
T1M[1:0]
R/W
0
0
3
GATE0
R/W
0
2
C/T0
R/W
0
1
0
T0M[1:0]
R/W
0
0
SFR Address = 0x89
Bit Name
Function
7
GATE1 Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND INT1 is active as defined by bit IN1PL in
register IT01CF (see SFR Definition 18.7).
6
C/T1 Counter/Timer 1 Select.
0: Timer: Timer 1 incremented by clock defined by T1M bit in register CKCON.
1: Counter: Timer 1 incremented by high-to-low transitions on external pin (T1).
5:4 T1M[1:0] Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Timer 1 Inactive
3
GATE0 Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND INT0 is active as defined by bit IN0PL in
register IT01CF (see SFR Definition 18.7).
2
C/T0 Counter/Timer 0 Select.
0: Timer: Timer 0 incremented by clock defined by T0M bit in register CKCON.
1: Counter: Timer 0 incremented by high-to-low transitions on external pin (T0).
1:0 T0M[1:0] Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Two 8-bit Counter/Timers
216
Rev. 1.0