C8051F80X_14 Datasheet, PDF (138/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
23. Port Input/Output
Digital and analog resources are available through 17 I/O pins (24-pin and 20-pin packages) or 13 I/O pins
(16-pin packages). Port pins P0.0–P1.7 can be defined as general-purpose I/O (GPIO) or assigned to one
of the internal digital resources as shown in Figure 23.4. Port pin P2.0 can be used as GPIO and is shared
with the C2 Interface Data signal (C2D). The designer has complete control over which functions are
assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in
the corresponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 23.5). The registers XBR0 and XBR1, defined in SFR Definition 23.1 and SFR Definition 23.2, are
used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 23.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Section “7. Electrical Characteristics” on page 39.
XBR0, XBR1,
PnSKIP Registers
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
Highest
Priority
Lowest
Priority
2
UART
4
SPI
2
SMBus
CP0
2
Outputs
Priority
Decoder
8
Digital
Crossbar
8
External Interrupts
EX0 and EX1
PnMDOUT,
PnMDIN Registers
P0
I/O
Cells
P1
I/O
Cells
SYSCLK
PCA
4
2
T0, T1
8
P0 _(P0.0-P0.7)
8
P1 _(P1.0-P1.7)
P2
I/O
Cells
*Note: P1.4-P1.7
are not available
on the 16-pin
packages.
To Analog Peripherals
(ADC0, CP0, VREF, XTAL)
To CS0
Figure 23.1. Port I/O Functional Block Diagram
P0.0
P0.7
P1.0
P1.7*
P2.0
138
Rev. 1.0