C8051F80X_14 Datasheet, PDF (153/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
Each Port has a corresponding PnSKIP register which allows its individual Port pins to be assigned to dig-
ital functions or skipped by the Crossbar. All Port pins used for analog functions or GPIO should have their
PnSKIP bit set to 1.
The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port
cell can be configured for analog or digital I/O. This selection is required even for the digital resources
selected in the XBRn registers, and is not automatic. The only exception to this is P2.0, which can only be
used for digital I/O.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings.
SFR Definition 23.7. P0: Port 0
Bit
7
6
5
4
3
2
1
0
Name
P0[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0x80; Bit-Addressable
Bit Name
Description
7:0 P0[7:0] Port 0 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Write
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
Read
0: P0.n Port pin is logic
LOW.
1: P0.n Port pin is logic
HIGH.
Rev. 1.0
153