C8051F80X_14 Datasheet, PDF (145/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
Port
P0
P1
Pin Number 0 1 2 3 4 5 6 7 0 1 2 3 4¹ 5¹ 6¹ 7¹ 0
Special
Function
Signals
TX0
RX0
SCK
MISO
MOSI
NSS²
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
Pin Skip ^{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0}
Settings
P0SKIP
P1SKIP
In this example, the crossbar is configured to assign the UART TX0 and
RX0 signals, the SPI signals, and the PCA signals. Note that the SPI
signals are assigned as multiple signals, and there are no pins skipped
using the P0SKIP or P1SKIP registers.
These boxes represent the port pins which are used by the peripherals
in this configuration.
1^st TX0 is assigned to P0.4
2^nd RX0 is assigned to P0.5
3^rd SCK, MISO, MOSI, and NSS are assigned to P0.0, P0.1, P0.2, and
P0.3, respectively.
4^th CEX0, CEX1, and CEX2 are assigned to P0.6, P0.7, and P1.0,
respectively.
All unassigned pins can be used as GPIO or for other non-crossbar
functions.
Notes:
1. P1.4-P1.7 are not available on 16-pin packages.
2. NSS is only pinned out when the SPI is in 4-wire mode.
Figure 23.5. Priority Crossbar Decoder Example 1—No Skipped Pins
Rev. 1.0
145