C8051F80X_14 Datasheet, PDF (48/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
8.3.2. Tracking Modes
The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion
start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM is left
at logic 0, a conversion will begin immediately, without the extra tracking time. For internal start-of-conver-
sion sources, the ADC will track anytime it is not performing a conversion. When the CNVSTR signal is
used to initiate conversions, ADC0 will track either when AD0TM is logic 1, or when AD0TM is logic 0 and
CNVSTR is held low. See Figure 8.2 for track and convert timing details. Delayed conversion mode is use-
ful when AMUX settings are frequently changed, due to the settling time requirements described in Section
“8.3.3. Settling Time Requirements” on page 49.
CNVSTR
(AD0CM[2:0]=1xx)
SAR
Clocks
AD0TM=1
SAR Clocks
A. ADC Timing for External Trigger Source
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15* 16 17
Track
Convert
Track
*Conversion Ends at rising edge of 15^th clock in 8-bit Mode
1 2 3 4 5 6 7 8 9 10 11 12* 13 14
AD0TM=0 N/C Track
Convert
N/C
Write '1' to AD0BUSY,
Timer 0, Timer 2, Timer 1 Overflow
(AD0CM[2:0]=000, 001, 010, 011)
*Conversion Ends at rising edge of 12^th clock in 8-bit Mode
B. ADC Timing for Internal Trigger Source
SAR
Clocks
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15* 16 17
AD0TM=1
Track
Convert
Track
*Conversion Ends at rising edge of 15^th clock in 8-bit Mode
SAR
Clocks
AD0TM=0
1 2 3 4 5 6 7 8 9 10 11 12* 13 14
Track or
Convert
Convert
Track
*Conversion Ends at rising edge of 12^th clock in 8-bit Mode
Figure 8.2. 10-Bit ADC Track and Conversion Example Timing
48
Rev. 1.0