C8051F80X_14 Datasheet, PDF (107/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
SFR Definition 18.3. EIE1: Extended Interrupt Enable 1
Bit
7
6
Name ^{Reserved Reserved}
Type
W
W
Reset
0
0
5
ECP0
R/W
0
4
EADC0
R/W
0
3
EPCA0
R/W
0
2
EWADC0
R/W
0
1
EMAT
R/W
0
0
ESMB0
R/W
0
SFR Address = 0xE6
Bit Name
Function
7 Reserved Must write 0.
6 Reserved Reserved.
Must write 0.
5 ECP0 Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 rising edge or falling edge interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF and CP0FIF flags.
4 EADC0 Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
3 EPCA0 Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
2 EWADC0 Enable Window Comparison ADC0 interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
1 EMAT Enable Port Match Interrupts.
This bit sets the masking of the Port Match event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
0 ESMB0 Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
Rev. 1.0
107