C8051F80X_14 Datasheet, PDF (22/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
RST/C2CK
VDD
GND
Power On
Reset
Reset
Debug /
Programming
Hardware
P2.0/C2D
CIP-51 8051
Controller Core
Flash Memory
‘F824, ‘F827: 8 kB
‘F830, ‘F833: 4 kB
256 Byte RAM
Peripheral
Power
Regulator
Core Power
XTAL1
XTAL2
SYSCLK
Precision
Internal
Oscillator
External
Clock
Circuit
System Clock
Configuration
Port I/O Configuration
Digital Peripherals
SFR
Bus
UART
Timers
0, 1
Timer 2 /
RTC
PCA/
WDT
SMBus
Priority
Crossbar
Decoder
SPI
Crossbar Control
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Analog
Peripherals
A
+
M
-
U
Comparator X
Capacitive 12 Channels
Sense
VREG Output
VDD
10-bit
500 ksps
ADC
VREF
A
M
U
X
(‘F824, ‘F830 Only)
VREG Output
VDD
12 Channels
Temp Sensor
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
P1.0
P1.1
P1.2
P1.3
P2.0/C2D
Figure 1.7. C8051F824, C8051F827, C8051F830, C8051F833 Block Diagram
22
Rev. 1.0