C8051F80X_14 Datasheet, PDF (155/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
SFR Definition 23.10. P0SKIP: Port 0 Skip
Bit
7
6
5
4
3
2
1
0
Name
P0SKIP[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xD4
Bit
Name
7:0 P0SKIP[7:0]
Function
Port 0 Crossbar Skip Enable Bits.
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
SFR Definition 23.11. P1: Port 1
Bit
7
6
5
4
3
2
1
0
Name
P1[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0x90; Bit-Addressable
Bit Name
Description
7:0 P1[7:0] Port 1 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Note: P1.4–P1.7 are not
available on 16-pin
packages.
Write
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
Read
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
Rev. 1.0
155