C8051F80X_14 Datasheet, PDF (125/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
21.2. Power-Fail Reset / V_DD Monitor
When a power-down transition or power irregularity causes V_DD to drop below V_RST, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 21.2). When V_DD returns
to a level above V_RST, the CIP-51 will be released from the reset state. Even though internal data memory
contents are not altered by the power-fail reset, it is impossible to determine if V_DD dropped below the level
required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V_DD monitor is
enabled and selected as a reset source after power-on resets. Its defined state (enabled/disabled) is not
altered by any other reset source. For example, if the V_DD monitor is disabled by code and a software reset
is performed, the V_DD monitor will still be disabled after the reset.
Important Note: If the V_DD monitor is being turned on from a disabled state, it should be enabled before it
is selected as a reset source. Selecting the V_DD monitor as a reset source before it is enabled and stabi-
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V_DD monitor and configuring it as a reset source from a disabled
state is shown below:
1. Enable the V_DD monitor (VDMEN bit in VDM0CN = 1).
2. If necessary, wait for the V_DD monitor to stabilize.
3. Select the V_DD monitor as a reset source (PORSF bit in RSTSRC = 1).
See Figure 21.2 for V_DD monitor timing; note that the power-on-reset delay is not incurred after a V_DD
monitor reset. See Section “7. Electrical Characteristics” on page 39 for complete electrical characteristics
of the V_DD monitor.
Rev. 1.0
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