C8051F80X_14 Datasheet, PDF (164/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
SFR Definition 24.2. CRC0IN: CRC Data Input
Bit
7
6
5
4
3
2
1
0
Name
CRC0IN[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xDD
Bit
Name
Function
7:0 CRC0IN[7:0] CRC0 Data Input.
Each write to CRC0IN results in the written data being computed into the existing
CRC result according to the CRC algorithm described in Section 24.1
SFR Definition 24.3. CRC0DATA: CRC Data Output
Bit
7
6
5
4
3
2
1
0
Name
CRC0DAT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xDE
Bit
Name
Function
7:0 CRC0DAT[7:0] CRC0 Data Output.
Each read or write performed on CRC0DAT targets the CRC result bits pointed to
by the CRC0 Result Pointer (CRC0PNT bits in CRC0CN).
164
Rev. 1.0