C8051F80X_14 Datasheet, PDF (109/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
SFR Definition 18.5. EIP1: Extended Interrupt Priority 1
Bit
7
6
Name ^{Reserved Reserved}
Type
W
W
Reset
0
0
5
PCP0
R/W
0
4
PPCA0
R/W
0
3
PADC0
R/W
0
2
PWADC0
R/W
0
1
PMAT
R/W
0
SFR Address = 0xF3
Bit Name
Function
7:6 Reserved Must write 0.
5 PCP0 Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 rising edge or falling edge interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
4 PPCA0 Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
3 PADC0 ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
2 PWADC0 ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
1 PMAT Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
0 PSMB0 SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
0
PSMB0
R/W
0
Rev. 1.0
109