C8051F80X_14 Datasheet, PDF (129/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
22. Oscillators and Clock Selection
C8051F80x-83x devices include a programmable internal high-frequency oscillator and an external oscilla-
tor drive circuit. The internal high-frequency oscillator can be enabled/disabled and calibrated using the
OSCICN and OSCICL registers, as shown in Figure 22.1. The system clock can be sourced by the exter-
nal oscillator circuit or the internal oscillator (default). The internal oscillator offers a selectable post-scaling
feature, which is initially set to divide the clock by 8.
Option 2 – RC Mode
VDD
OSCICL
OSCICN
CLKSEL
XTAL2
Option 4 – CMOS Mode
XTAL2
Option 1 – Crystal Mode
XTAL1
10M
XTAL2
Option 3 – C Mode
XTAL2
EN
Programmable
Internal Clock
Generator
n
Clock Divider
Input
Circuit
OSC
CLKRDY
SYSCLK
n
Clock Divider
OSCXCN
Figure 22.1. Oscillator Options
22.1. System Clock Selection
The system clock source for the MCU can be selected using the CLKSEL register. The clock selected as
the system clock can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. When switching between two clock divide
values, the transition may take up to 128 cycles of the undivided clock source. The CLKRDY flag can be
polled to determine when the new clock divide value has been applied. The clock divider must be set to
"divide by 1" when entering Suspend mode. The system clock source may also be switched on-the-fly. The
switchover takes effect after one clock period of the slower oscillator.
Rev. 1.0
129