C8051F80X_14 Datasheet, PDF (29/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
Table 3.1. Pin Definitions for the C8051F80x-83x (Continued)
Name
Pin
Pin
Pin
Type Description
QSOP-24 QFN-20 SOIC-16
P0.5
21
16
14 D I/O or Port 0.5.
A In
P0.6/
20
15
13 D I/O or Port 0.6.
A In
CNVSTR
D In ADC0 External Convert Start or IDA0 Update
Source Input.
P0.7
19
14
12 D I/O or Port 0.7.
A In
P1.0
18
13
11 D I/O or Port 1.0.
A In
P1.1
17
12
10 D I/O or Port 1.1.
A In
P1.2
16
11
9
D I/O or Port 1.2.
A In
P1.3
15
10
8
D I/O or Port 1.3.
A In
P1.4
14
9
D I/O or Port 1.4.
A In
P1.5
11
8
D I/O or Port 1.5.
A In
P1.6
10
7
D I/O or Port 1.6.
A In
P1.7
9
6
D I/O or Port 1.7.
A In
NC 1, 12, 13,
24
No Connection.
Rev. 1.0
29