C8051F80X_14 Datasheet, PDF (188/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
SFR Definition 26.2. SMB0CN: SMBus Control
Bit
7
6
5
4
3
2
1
0
Name ^{MASTER TXMODE STA}
STO
ACKRQ ARBLOST ACK
SI
Type
R
R
R/W
R/W
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC0; Bit-Addressable
Bit Name
Description
7 MASTER _{SMBus Master/Slave}
Indicator. This read-only bit
indicates when the SMBus is
operating as a master.
6 TXMODE _{SMBus Transmit Mode}
Indicator. This read-only bit
indicates when the SMBus is
operating as a transmitter.
5
STA _{SMBus Start Flag.}
4
STO _{SMBus Stop Flag.}
3 ACKRQ _{SMBus Acknowledge}
Request.
2 ARBLOST _{SMBus Arbitration Lost}
Indicator.
1
ACK _{SMBus Acknowledge.}
Read
Write
0: SMBus operating in
N/A
slave mode.
1: SMBus operating in
master mode.
0: SMBus in Receiver
N/A
Mode.
1: SMBus in Transmitter
Mode.
0: No Start or repeated 0: No Start generated.
Start detected.
1: Start or repeated Start
detected.
1: When Configured as a
Master, initiates a START
or repeated START.
0: No Stop condition
0: No STOP condition is
detected.
transmitted.
1: Stop condition detected 1: When configured as a
(if in Slave Mode) or pend- Master, causes a STOP
ing (if in Master Mode). condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
0: No Ack requested
N/A
1: ACK requested
0: No arbitration error.
N/A
1: Arbitration Lost
0: NACK received.
1: ACK received.
0: Send NACK
1: Send ACK
0
SI
SMBus Interrupt Flag.
0: No interrupt pending ^{0: Clear interrupt, and initi-}
This bit is set by hardware 1: Interrupt Pending
under the conditions listed in
Table 15.3. SI must be cleared
ate next state machine
event.
1: Force interrupt.
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
188
Rev. 1.0