C8051F80X_14 Datasheet, PDF (75/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
SFR Definition 13.1. CS0CN: Capacitive Sense Control
Bit
7
6
5
4
3
2
Name ^CS0EN
CS0INT CS0BUSY CS0CMPEN
Type ^R/W
R
R/W
R/W
R/W
R
Reset
0
0
0
0
0
0
1
0
CS0CMPF
R
R
0
0
SFR Address = 0xB0; Bit-Addressable
Bit
Name
Description
7
CS0EN CS0 Enable.
0: CS0 disabled and in low-power mode.
1: CS0 enabled and ready to convert.
6
Unused Read = 0b; Write = Don’t care
5
CS0INT CS0 Interrupt Flag.
0: CS0 has not completed a data conversion since the last time CS0INT was
cleared.
1: CS0 has completed a data conversion.
This bit is not automatically cleared by hardware.
4 CS0BUSY CS0 Busy.
Read:
0: CS0 conversion is complete or a conversion is not currently in progress.
1: CS0 conversion is in progress.
Write:
0: No effect.
1: Initiates CS0 conversion if CS0CM[2:0] = 000b, 110b, or 111b.
3 CS0CMPEN CS0 Digital Comparator Enable Bit.
Enables the digital comparator, which compares accumulated CS0 conversion
output to the value stored in CS0THH:CS0THL.
0: CS0 digital comparator disabled.
1: CS0 digital comparator enabled.
2:1
Unused Read = 00b; Write = Don’t care
0 CS0CMPF CS0 Digital Comparator Interrupt Flag.
0: CS0 result is smaller than the value set by CS0THH and CS0THL since the last
time CS0CMPF was cleared.
1: CS0 result is greater than the value set by CS0THH and CS0THL since the last
time CS0CMPF was cleared.
Note: On waking from suspend mode due to a CS0 greater-than comparator event, the CS0CN register
should be accessed only after at least two system clock cycles have elapsed.
Rev. 1.0
75