C8051F80X_14 Datasheet, PDF (76/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
SFR Definition 13.2. CS0CF: Capacitive Sense Configuration
Bit
7
6
5
4
3
2
1
0
Name
CS0CM[2:0]
CS0ACU[2:0]
Type
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x9E
Bit
Name
7
Unused
6:4 CS0CM[2:0]
3
Unused
2:0 CS0ACU[2:0]
Description
Read = 0b; Write = Don’t care
CS0 Start of Conversion Mode Select.
000: Conversion initiated on every write of 1 to CS0BUSY.
001: Conversion initiated on overflow of Timer 0.
010: Conversion initiated on overflow of Timer 2.
011: Conversion initiated on overflow of Timer 1.
100: Reserved.
101: Reserved.
110: Conversion initiated continuously after writing 1 to CS0BUSY.
111: Auto-scan enabled, conversions initiated continuously after writing 1 to
CS0BUSY.
Read = 0b; Write = Don’t care
CS0 Accumulator Mode Select.
000: Accumulate 1 sample.
001: Accumulate 4 samples.
010: Accumulate 8 samples.
011: Accumulate 16 samples
100: Accumulate 32 samples.
101: Accumulate 64 samples.
11x: Reserved.
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Rev. 1.0