C8051F80X_14 Datasheet, PDF (28/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051F80x-83x
Name
GND
V_DD
RST/
C2CK
P2.0/
C2D
Pin
Pin
Pin
QSOP-24 QFN-20 SOIC-16
5
2
4
6
3
5
7
4
6
8
5
7
Type Description
Ground.
This ground connection is required. The center
pad may optionally be connected to ground as
well on the QFN-20 packages.
Power Supply Voltage.
D I/O
Device Reset. Open-drain output of internal
POR or V_DD monitor. An external source can ini-
tiate a system reset by driving this pin low for at
least 10 µs.
D I/O Clock signal for the C2 Debug Interface.
D I/O Bi-directional data signal for the C2 Debug Inter-
face. Shared with P2.0 on 20-pin packaging and
P2.4 on 24-pin packaging.
D I/O Bi-directional data signal for the C2 Debug Inter-
face. Shared with P2.0 on 20-pin packaging and
P2.4 on 24-pin packaging.
P0.0/
4
1
3
D I/O or Port 0.0.
A In
VREF
A In External VREF input.
P0.1
3
20
2
D I/O or Port 0.1.
A In
P0.2/
2
19
1
D I/O or Port 0.2.
A In
XTAL1
A In External Clock Input. This pin is the external
oscillator return for a crystal or resonator.
P0.3/
23
18
16 D I/O or Port 0.3.
A In
XTAL2
A I/O or External Clock Output. For an external crystal or
D In ^{resonator, this pin is the excitation driver. This}
pin is the external clock input for CMOS, capaci-
tor, or RC oscillator configurations.
P0.4
22
17
15 D I/O or Port 0.4.
A In
28
Rev. 1.0