C8051F80X_14 Datasheet, PDF (157/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
SFR Definition 23.14. P1SKIP: Port 1 Skip
Bit
7
6
5
4
3
2
1
0
Name
P1SKIP[7:0]
Type
R/W
Reset
0*
0*
0*
0*
0
0
0
0
SFR Address = 0xD5
Bit
Name
7:0 P1SKIP[7:0]
Function
Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
Note: P1.4–P1.7 are not available on 16-pin packages, with the reset value of 1111b for
P1SKIP[7:4].
SFR Definition 23.15. P2: Port 2
Bit
7
6
5
4
3
2
1
0
Name
P2[0]
Type
R
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
1
SFR Address = 0xA0; Bit-Addressable
Bit Name
Description
7:1 Unused Unused.
0 P2[0] Port 2 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Write
Don’t Care
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
Read
0000000b
0: P2.0 Port pin is logic
LOW.
1: P2.0 Port pin is logic
HIGH.
Rev. 1.0
157