C8051F80X_14 Datasheet, PDF (165/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
SFR Definition 24.4. CRC0AUTO: CRC Automatic Control
Bit
7
6
5
4
3
2
1
0
Name ^{AUTOEN CRCCPT Reserved}
CRC0ST[4:0]
Type
R/W
Reset
0
1
0
0
0
0
0
0
SFR Address = 0xD2
Bit
Name
7
AUTOEN
6
CRCCPT
5
Reserved
4:0 CRC0ST[4:0]
Function
Automatic CRC Calculation Enable.
When AUTOEN is set to 1, any write to CRC0CN will initiate an automatic CRC
starting at Flash sector CRC0ST and continuing for CRC0CNT sectors.
Automatic CRC Calculation Complete.
Set to 0 when a CRC calculation is in progress. Code execution is stopped during
a CRC calculation, therefore reads from firmware will always return 1.
Must write 0.
Automatic CRC Calculation Starting Flash Sector.
These bits specify the Flash sector to start the automatic CRC calculation. The
starting address of the first Flash sector included in the automatic CRC calculation
is CRC0ST x 512.
SFR Definition 24.5. CRC0CNT: CRC Automatic Flash Sector Count
Bit
7
6
5
4
3
2
1
0
Name
CRC0CNT[5:0]
Type
R
R
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xD3
Bit
Name
Function
7:6
Unused Read = 00b; Write = Don’t Care.
5:0 CRC0CNT[5:0] Automatic CRC Calculation Flash Sector Count.
These bits specify the number of Flash sectors to include when performing an
automatic CRC calculation. The base address of the last flash sector included in
the automatic CRC calculation is equal to (CRC0ST + CRC0CNT) x 512.
Rev. 1.0
165