C8051F80X_14 Datasheet, PDF (92/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
15. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
C8051F80x-83x device family is shown in Figure 15.1
PROGRAM/DATA MEMORY
(FLASH)
C8051F80x and C8051F810/1
0x3FFF
Lock Byte
0x3FFE
16 kB Flash
0x0000
(In-System
Programmable in 512
Byte Sectors)
C8051F812/3/4/5/6/7/8/9
and C8051F82x
0x1FFF
Lock Byte
0x1FFE
8 kB Flash
0x0000
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Lower 128 RAM
(Direct and Indirect
Addressing)
0xFFFF
EXTERNAL DATA ADDRESS SPACE
C8051F80x, C8051F81x, and
C8051F820/1/2/3 Only
0x0FFF
0x0FFE
C8051F830/1/2/3/4/5
Lock Byte
4 kB Flash
0x0000
(In-System
Programmable in 512
Byte Sectors)
Same 256 bytes as from
0x0000 to 0x01FF, wrapped
on 256-byte boundaries
0x0100
0x00FF
0x0000
XRAM - 256 Bytes
(accessable using MOVX
instruction)
Figure 15.1. C8051F80x-83x Memory Map
92
Rev. 1.0